PAI MCQ's SET-6
1. The feature of Pentium 4 is
a) works based on Net Burst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
Answer: d
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
Answer: c
3. The front module of Pentium 4
consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
Answer: d
4. The unit that decodes the instructions concurrently and translate them into
micro-operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
Answer: b
5. In complex instructions, when the
instruction needs to be translated into more than 4 micro-operations, then the
decoder transfers the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: c
6. The unit that does not store the
instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Answer: a
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
Answer: d
8. The unit that predicts the
locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: b
9. If complex instructions like
interrupt handling, string manipulation appear, then the control from trace
cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
10. After the micro-ops are issued
by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Answer: a
11. The mechanism to provide
protection, that is accomplished with the help of read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
Answer: a
12. The Local descriptor table (LDT)
and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Answer: c
13. The mechanism that is
accomplished using descriptor usages limitations, and rules of privilege check
is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Answer: b
14. The mechanism that is executed
at certain privilege levels, determined by CPL (Current Privilege Level) and
I/O privilege level (IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
Answer: c
15. If CPL is not of the required
privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) none of the mentioned
Answer: c
16. If CPL is greater than zero,
then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
Answer: c
17. The condition, “CPL not equals
to zero” satisfies, when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) all of the mentioned
Answer: d
18. While executing the instruction
IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) all of the mentioned
Answer: c
19. The instruction at which the
exception is generated, but the processor extension registers contain the
address of failing instruction is
a) LTR
b) INS
c) CTS
d) ESC
Answer: d
20. The exception that has no error
code on stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
Answer: b
