PAI MCQ's Set-1
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Answer: d
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Answer: c
3. The number of debug registers that are available in 80386, for hardware debugging and control is
a) 2
b) 4
c) 8
d) 16
b) 4
c) 8
d) 16
Answer: c
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Answer: d
5. The 80386 enables itself to organize the available physical memory into pages, which is known as a) segmentation
b) paging
c) memory division
d) none of the mentioned
Answer: b
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Answer: d
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Answer: c
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Answer: b
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Answer: a
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Answer: d
11. Which of the units is not a part of internal architecture of 80386?
a) central processing unit
b) memory management unit
c) bus interface unit
d) none of the mentioned
Answer: d
12. The central processing unit has a sub-division of
a) memory unit and control unit
b) memory unit and ALU
c) execution unit and instruction unit
d) execution unit and memory unit
Answer: c
13. The unit that is used for handling data, and calculate offset address is
a) memory management unit
b) execution unit
c) instruction unit
d) bus interface unit
Answer: b
14. The unit that decodes the opcode bytes, received from the 16-byte instruction code queue is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: c
15. The unit that increases the speed of all shift and rotate operations is
a) memory management unit
b) execution unit
c) instruction unit
d) barrel shifter
Answer: d
16. The memory management unit consists of
a) segmentation unit
b) paging unit
c) segmentation and paging units
d) none of the mentioned
Answer: c
17. The segmentation unit allows
a) maximum size of 4GB segments
b) use of segment address components
c) use of offset address components
d) all of the mentioned
Answer: d
18. The unit that organizes the physical memory, in terms of pages of 4KB size each is
a) segmentation unit
b) execution unit
c) paging unit
d) instruction unit
Answer: c
19. The paging unit works under the control of
a) memory management unit
b) segmentation unit
c) execution unit
d) instruction unit
Answer: b
20. The unit that provides a four level protection mechanism, for system’s code and data against application program is
a) central processing unit
b) segmentation unit
c) bus interface unit
d) none of the mentioned
Answer: b
