PAI MCQ's SET-2

21. The unit that has a prioritizer to resolve the priority of the various bus requests is

a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit

Answer: c 


22. The unit that interfaces the internal data bus with the system bus is
a) bus sizing unit
b) data buffer
c) bus control unit
d) execution unit

Answer: b 


23. The unit that drives the bus enable and address signals A0-A31 is
a) bus sizing unit
b) bus driving unit
c) address driver
d) bus driver

Answer: c


24. Which of the following pin when activated, allows address pipelining?
a) ADS
b) NA
c) AP
d) none of the mentioned

Answer: b 


25. The signal that is used to insert WAIT states in a bus cycle in 80386 is
a) HOLD
b) HLDA
c) READY
d) PEREQ
Answer: c


26. The signal which indicates to the CPU, to fetch a data word for the coprocessor is
a) READY
b) NMI
c) HLDA
d) PEREQ

Answer: d


27. The pipeline and dynamic bus sizing units handle
a) data signals
b) address signals
c) control signals
d) all of the mentioned

Answer: c 


28. The 16-bit registers are available with their extended size of 32 bits, by adding the registers with a prefix of
a) X
b) E
c) 32
d) XX

Answer: b 


29. In a 32-bit register, ESP, the lower 16-bits of the register can be represented by
 a) LSP
 b) FSP
 c) SP
 d) none of the mentioned

Answer: c 


30. Which of the following is a data segment register of 80386?
a) ES
b) FS
c) GS
d) all of the mentioned

Answer: d 


31. The register width used by the 32-bit addressing modes is
a) 8 bits
b) 16 bits
c) 32 bits
d) all of the mentioned

Answer: d 


32. The flag that is additional in flag register of 80386, compared to that of 80286 is
a) VM flag
b) RF flag
c) VM and RF flag
d) none of the mentioned

Answer: c 


33. The VM (virtual mode) flag is to be set, only when 80386 is in
a) virtual mode
b) protected mode
c) either virtual or protected mode
d) all of the mentioned

Answer: b


34. In protected mode of 80386, the VM flag is set by using
a) IRET instruction
b) task switch operation
c) IRET instruction or task switch operation
d) none of the mentioned

Answer: c


35. During the instruction cycle of 80386, any debug fault can be ignored if
a) VM flag is set
b) VM flag is cleared
c) RF is cleared
d) RF is set

Answer: d 


36. The RF is not automatically reset after the execution of
a) IRET
b) POPA
c) IRET and POPF
d) IRET and PUSHF

Answer: c 


37. The segment descriptor register is used to store
a) attributes
b) limit address of segments
c) base address of segments
d) all of the mentioned

Answer: d 


38. The 32-bit control register, that is used to hold global machine status, independent of the executed task is
a) CR0
b) CR2
c) CR3
d) all of the mentioned

Answer: d 


39. The descriptor table that the 80386 supports is
a) GDT (Global descriptor table)
b) IDT (Interrupt descriptor table)
c) LDT (Local descriptor table)
d) TSS (Task state segment descriptor)
e) all of the mentioned

Answer: e 


40. The registers that are together, known as system address registers are
a) GDTR and IDTR
b) IDTR and LDTR
c) TR and GDTR
d) LDTR and TR

Answer: a